成果类别 | 参考成果 | 代表性成果 （项目、论文、专利、成果奖项） |
AI辅助EDA工具 | 人工智能辅助光刻工艺建模、热点检测、掩膜拆分、器件建模、电路仿真等DTCO工具链 | 项目：国家科技重大专项“AMOLED显示面板多工艺协同设计与数字化试验平台研发及验证” 论文： [1] Hongwei Yao, Xinyu Zou, Xinyu Shang, Jianing Zhang, Xiaojin Li, Yang Shen, Ziyu Liu, Bingyi Ye, Yuhang Zhang, Yanling Shi, Yabin Sun, “SMS-EMOA-Driven Multi-Objective Design-Technology Co-Optimization for 5 nm Gate-All-Around Transistors”, IEEE Transactions on Electron Devices, 2026 [2] Yuhang Zhang, Qing Zhang, Yang Shen, Bingyi Ye, Xiaojin Li, Yabin Sun, Yanling Shi, Yongfu Li, “ATMAD: Agile Transistor Compact Modeling with Parameter Extraction Based on Automatic Differentiation”, ACM Transactions on Design Automation of Electronic Systems, 2026 [3] Fu Gong, Xinyu Zou, Yuhang Zhang, Yang Shen, Bingyi Ye, Xiaojin Li, Shaoqiang Chen, Fei Lu, Xinyu Dong, Ziyu Liu, Yabin Sun, “A Physics Constrained Neural Network Method for Compact Modeling of Semiconductor Devices”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2026 [4] Qing Zhang, Yuhang Zhang, Rui Chen, Wei Lu, Huajie Huang, Zhiqiang Li, Yongfu Li, “pFed-Litho: Lithography Modeling With a Personalized Federated Learning Based Framework”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 [5] Xinyu Shang, Tianyi Xu, Hongwei Yao, Bingyi Ye, Yang Shen, Xiaojin Li, Yabin Sun, Yuhang Zhang, “U-WNO-ILT: U-Net Enhanced Wavelet Neural Operator with Spectral-Spatial Decoupling for Inverse Lithography”, International Symposium of Electronics Design Automation (ISEDA), 2026 [6] Jianing Zhang, Jiaqi Dou, Yang Shen, Bingyi Ye, Xiaojin Li, Yanling Shi, Yuhang Zhang, Yabin Sun, “APEX: Automating Parameter Extraction of Compact Models with Differential Neural Network Approximation”, International Symposium of Electronics Design Automation (ISEDA), 2025 [7] Jiaqi Dou, Jianing Zhang, Bingyi Ye, Yang Shen, Xiaojin Li, Yanling Shi, Yuhang Zhang, Yabin Sun, “MALTS: A Multi-Agent Large Language Model-Based Layout-to-TCAD Structure Synthesizer”, International Symposium of Electronics Design Automation (ISEDA), 2025 [8] Yifan Guo, Jiawei Chen, Yexin Li, Yunxiang Zhang, Qing Zhang, Yuhang Zhang, Yongfu Li, “SEDG: Stitch-Compatible End-to-End Layout Decomposition Based on Graph Neural Network”, Design, Automation & Test in Europe Conference (DATE), 2025 |
先进工艺器件 | 先进节点Fin/GAA工艺、器件、寄生及SPICE模型开发与协同优化设计 | 项目： 1.上海市科委“探索者计划” 先进工艺中后道寄生精准表征、测试及建模； 2.上海市科委“探索者计划” 背部供电FinFET中后道寄生提取建模、测试结构开发及寄生导向优化 3.国家科技重大专项(2016ZX02301003): 22nm FD-SOI MOSFET栅围寄生效应及建模； 4.国家自然科学基金面上项目，非对称侧墙三维环栅可重构晶体管：机理、模型及工艺研究； 5.上海市科委基础研究计划 “跨尺度热仿真驱动三维集成芯片内外层协同高效散热技术研究 6.上海市科委“探索者计划” 硅基毫米波太赫兹建模及IP设计验证 论文： (1) Yuhao Zhou, Yang Shen, Yuhang Zhang, Biyi Ye, Yabin Sun*, Assessment of capacitorless DRAM Based on Stacked Nanosheet Feedback Field-Effect Transistors With Tree-Type Channe, IEEE Transactions on Electron Devices, 2026 (2) Xinyu Zou, Yuhao Zhou, Fu Gong, Ziyu Liu, Xiaojin Li, Yang Shen, Bingyi Ye, Yuhang Zhang, Yanling Shi and Yabin Sun*, Novel triple gate nanosheet RFET with embeded SiGe surrounding channel for enhanced on-state current, IEEE Transactions on Electron Devices, 2026 (3) Chao Wang, Yang Shen, Yuhang Zhang, Bingyi Ye, Xaioajin Li, Ziyu Liu, Yanling Shi, Yabin Sun*, TCAD simulation od Reconfigurable Field-effect Transistor with Toothed Spacer to improve ON-current, IEEE Transactions on Electron Devices, 2025 (4) Chao Wang, Yang Shen, Yuhang Zhang, Bingyi Ye, Xaioajin Li, Ziyu Liu, Yanling Shi, Yabin Sun*, TCAD simulation od Reconfigurable Field-effect Transistor with Toothed Spacer to improve ON-cirrent, IEEE Transactions on Electron Devices, 2025 (5) Jianing Zhao, Xinyu Zou, Yang Shen*, Yuhang Zhang, Bingyi Ye, Xiaojin Li, Ziyu Liu*, Yanling Shi, Shaoqiang Chen, Fei Lu, Xinyu Dong and Yabin Sun*, Novel Complementary Field-Effect Transistors with Tree-type Channel for 3nm Technology Node, IEEE Transactions on Electron Devices, 2025 (6) Xinyu Zou, Fu Gong, Mengge Jin, Ziyu Liu, Xiaojin Li, Yang Shen*, Bingyi Ye, Yuhang Zhang, Yanling Shi, Shaoqiang Chen, and Yabin Sun*, Evaluation of 1T-DRAM Based on Novel Triple-Gate Nanosheet RFET with Surrounded SiGe Channel, IEEE Transactions on Electron Devices, 2025 (7) Hongbo Ye, Junfeng Hu, Chao Wang, Xiaojin Li, Yanling Shi, Zhiagng Mao, and Yabin Sun*, Novel Reconfigurable Transistor with Extended Source/Drain beyond 3nm Technology Node, IEEE Transactions on Electron Devices 2024, 71(4), 2265-2270 (8) Chao Wang, Junfeng Hu, Ziyu Liu*, Xiaojin Li, Yanling Shi and Yabin Sun*, TCAD simulations of Reconfigurable Field-Effect Transistor with Embedded-Fin-Contact to Improve ON-current, IEEE Transactions on Electron Devices 2024, 71(5), 2849-2855 |
可靠性 | 与华大九天合作开发HRMI+OMI模型；电热模型及热计算应用于华为海思基站芯片开发 | 李小进老师方向 |
高速有线通信芯片设计 | 提出了切片式连续时间线性均衡器（Slice-based CTLE）电路、基于预失真相位插值器的八相时钟架构，设计并实现了首个224Gb/s XSR接收机芯片（ISSCC 2025）。 设计并实现了首个40GHz单片网络分析仪芯片（ISSCC 2025）。 | 项目： 1．国自然青年科学基金（C类），面向数据中心光互联的高能效收发机关键技术，26.1-28.12 2.上海市启明星培育项目（扬帆专项），超高速有线接收机模拟前端关键技术研究，24.12-27.11 论文： 1.Bingyi Ye, Tianchen Ye, Tianyuan Zhong, Zhiwen Huang, Lei Shen, Boyang Zhang, Dunshan Yu, Yandong He, Weixin Gai, “A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS,” ISSCC, 2025. 2.Guangdong Wu*, Yuanliang Li*, Bingyi Ye*, Fangzhu Li, Xin Liu, Haowei Niu, Ruixu Wang, Dunshan Yu, Weixin Gai, “A 99.5mW/port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS,” ISSCC, 2025 (*Equally Credited Authors). 3.Changjun Zhao*, Haoren Zhou*, Hangyu He, Tengyang Liu, Xiaojin Li, Yang Shen, Yuhang Zhang, Yanling Shi, Bingyi Ye, Yabin Sun,“A 5.7-mW 9-GHz 8-Bit Twin-Pi with a Digitally-Controlled Weighted Summer in 28-nm CMOS,”ISCAS, 2026. 4.Hangyu He, Yang Shen, Yuhang Zhang, Xiaojin Li, Yanling Shi, Bingyi Ye, Yabin Sun,“A Crossed Bond-Wire Structure for High-Speed Differential Interconnects Achieving 27% Reduction in Insertion Loss at 56 GHz,” ISCAS, 2026. 5.Zhiwen Huang*, Zhifei Wang*, Bingyi Ye, Tianchen Ye, Dunshan Yu, Wei Wang, Weixin Gai, “A 112Gb/s/wire Single-Ended Simultaneous Bi-Directional Transceiver with Dynamic Equalizer for Die-to-Die Interface in 28nm CMOS,” ISSCC, 2026. 6.Zhifei Wang, Zhiwen Huang, Tianchen Ye, Bingyi Ye, Fangzhu Li, Wei Wang, Dunshan Yu, Weixin Gai,“A 64Gb/s/wire 10.5Tb/s/mm/layer Single-Ended Simultaneous Bi-Directional Transceiver with Echo and Crosstalk Cancellation for a Die-to-Die Interface in 28nm CMOS,” ISSCC, 2025. 7.Boyang Zhang*, Tianchen Ye*, Shuaizhe Ma, Tianyuan Zhong, Xin Liu, Fangzhu Li, Bingyi Ye, Dan Li, Weixin Gai, “A 50Gb/s Burst-Mode NRZ Receiver with 5-Tap FFE, 7-Tap DFE and 15ns Lock Time in 28nm CMOS for Symmetric 50G-PON,” ISSCC, 2025. 专利： 1.一种基于信号延迟的交织采样保持电路，202510944850.5 2.一种高带宽引线键合结构，202510041895.1 3.一种高带宽差分引线键合结构，202510042223.2 |
射频毫米波芯片 | 44uW 433MHz超低功耗背散射标签芯片（华东师大首篇ISSCC）；77GHz 8TX-8RX高性能全集成CMOS雷达芯片（华东师大第二篇ISSCC） | 张润曦老师方向 |
半导体激光器 | 国际首个绿光氮化镓VCSEL室温单模连续激射；脉宽~70ps激光器驱动芯片（国际领先）；绝对值EL技术；转换效率7.56%硒硫化锑薄膜太阳能电池 | 陈少强老师方向 |
新型原子级器件 | 纳米尺度二维电子器件、新型存储器件 | 项目： 1．国自然青年科学基金（C类），基于忆阻器镜像堆叠结构的单器件逻辑，26.1-28.12 论文： (1) Shen Yang, Zhang Z, et al. A valuable and low-budget process scheme of equivalized 1 nm technology node based on 2D materials[J]. Nano-Micro Letters, 2025, 17(191). (IF：31.6) (2) Shen Yang, Dong Z, Sun Y, et al. The trend of 2D transistors toward integrated circuits: scaling down and new mechanisms[J]. Advanced Materials, 2022, 34(48): 2201916. (Cover article, IF：30.2) (3) Wu F#, Tian H#, Shen Yang#, et al. Vertical MoS2 transistors with sub-1-nm gate lengths[J]. Nature, 2022, 603(7900): 259-264.(IF：50.5) (4) Shen Yang*, Wang Z, Li C, Zhao Y, Ye B, Zhang Y, Tian H*, Sun Y*. Projected performance of nanowire transistor with sub-1nm gate length[J]. IEEE Electron Device Letter. (IF：4.9) (5) Shen Yang, Gao J, Guo Z, et al. RRAM mirrored and RRAM-transistor hybrid single device logic gates based on two-dimensional materials[J]. IEEE Electron Device Letters, 2023. (IF：4.9) (6) Shen Yang, Pan Z, Guo Z, et al. RRAM-based single device for vector multiplication and multi-bit storage with ultra-high area efficiency[J]. IEEE Transactions on Electron Devices, 2025. (IF：2.9) 专利： (1)场效应晶体管及其制备方法, 202310434922.2 (2)垂直顶栅二维薄膜场效应晶体管、电子设备及方法, 202311491847.X (3)一种单层十字交叉二维沟道逻辑器件, 202511350014.0 (4)具有亚1纳米栅极长度的碳纳米管环栅场效应晶体, 202511671723.9 (5)基于忆阻器和晶体管的逻辑门器件、控制方法和电路, 202311015247.6，已授权 (6)一种基于RRAM的堆叠型单器件及其实现2-bit向量乘积的方法, 202511423380.4 (7)基于忆阻器镜像堆叠的异或门逻辑器件及制备、使用方法, 202511423397.X |
